| dc.date.accessioned | 2021-01-27T14:55:09Z | |
| dc.date.available | 2021-01-27T14:55:09Z | |
| dc.date.issued | 2019-11 | |
| dc.identifier | doi:10.17170/kobra-202101193001 | |
| dc.identifier.uri | http://hdl.handle.net/123456789/12451 | |
| dc.language.iso | eng | eng |
| dc.rights | Urheberrechtlich geschützt | |
| dc.rights.uri | https://rightsstatements.org/page/InC/1.0/ | |
| dc.subject.ddc | 620 | |
| dc.subject.ddc | 004 | |
| dc.title | Development, Verification and Analysis of a Fault Injection Tool for Improving Dependability of FPGA Systems | eng |
| dc.type | Dissertation | |
| dcterms.abstract | Field Programmable Gate Array (FPGA) has been involved in various applications in the last couple of decades, such as aerospace, biomedical instrumentation, safety-critical systems, and spacecraft, due to their remarkable features. These features include parallelism, reconfiguration, self-healing capabilities, availability, low cost and low design turn-around time. FPGA devices are sensitive to Single Event Effects (SEE), which can be caused by various sources, such as α-particles, cosmic rays, atmospheric neutrons, heavy-ion radiations and electromagnetic radiations (x-rays or gamma rays). When a charged particle hits a critical node of FPGA-based design, it generates the transient pulse which can produce permanent or transient faults. Owing to technology scaling, testability, dependability and guaranteeing an acceptable degree of reliability are very challenging tasks.
Fault injection is the most well-known technique used in the evaluation of fault effects, verification and the dependability of a design. FPGA designs are mostly written in HDL, and a bit-stream file is generated, which is downloaded into the FPGA chip to implement the design. Fault injection can take place on each stage of the development stage. These tools for FPGA designs are classified into emulation and simulation-based techniques. Generally, the fault injection tool consists of three main components, i.e. fault list manager, fault injection manager and result analyser. The RASP-FIT tool is proposed and developed in Matlab, which helps design and test engineers to perform Verilog code-modification for fault injection analysis. This tool obtains compact test vectors, calculates fault coverage, and evaluates hardness analysis which finds the sensitive locations of the design to improve reliability directly at the code level.
Fault tolerance is the ability of a system to operate generally in the presence of faults. Triple Modular Redundancy (TMR) technique is one of the most popular methods used for FPGA designs. Building this triplication scheme is a non-trivial task and requires much time and effort to alter the code of the design. The RASP-TMR tool is developed in Matlab and presented that has functionalities to take a synthesizable Verilog design file as an input, parses the design and triplicates it. The tool generates the synthesizable design that facilitates the user to evaluate and verify the TMR design for FPGA-based systems. Both tools have a user-friendly graphical user interface. | eng |
| dcterms.accessRights | open access | |
| dcterms.alternative | Entwicklung, Überprüfung und Analyse eines Fehlers Injektionswerkzeug zur Verbesserung der Zuverlässigkeit von FPGAs Systeme | ger |
| dcterms.creator | Khatri, Abdul Rafay | |
| dcterms.dateAccepted | 2020-11-19 | |
| dcterms.extent | xxiv, 184 Seiten | |
| dc.contributor.corporatename | Kassel, Universität Kassel, Fachbereich Elektrotechnik / Informatik | ger |
| dc.contributor.referee | Börcsök, Josef (Prof. Dr.) | |
| dc.contributor.referee | Hillmer, Hartmut (Prof. Dr.) | |
| dc.subject.swd | Field programmable gate array | ger |
| dc.subject.swd | Fehleranalyse | ger |
| dc.subject.swd | Verifikation | ger |
| dc.subject.swd | Zuverlässigkeit | ger |
| dc.subject.swd | Designwissenschaft <Informatik> | ger |
| dc.type.version | publishedVersion | |
| kup.iskup | false | |
